V9958

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Revision as of 17:30, 4 December 2023 by WikiSysop (talk | contribs) (Created page with "'''VDP Video Display Processor''' =Pinout= <pre> SDIP64-750mil +---\/---+ GND | 1 64| XTAL2 *DHCLR | 2 63| XTAL1 *DLCLK | 3 62| *RAS *VRESET | 4 61| *CAS0 *HSYNC | 5 60| *CAS1 *CSYNC | 6 59| *CASX BLEO | 7 58| VDD CPUCLK/*VDS | 8 57| R/*W *RESET | 9 56| AD7 *YS |10 55| AD6 CBDR |11 54| AD5 C7 |12 53| AD4 C6 |13 52| AD3 C5 |1...")
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VDP Video Display Processor

Pinout

           SDIP64-750mil
            +---\/---+
        GND | 1    64| XTAL2
     *DHCLR | 2    63| XTAL1
     *DLCLK | 3    62| *RAS
    *VRESET | 4    61| *CAS0
     *HSYNC | 5    60| *CAS1
     *CSYNC | 6    59| *CASX
       BLEO | 7    58| VDD
CPUCLK/*VDS | 8    57| R/*W
     *RESET | 9    56| AD7
        *YS |10    55| AD6
       CBDR |11    54| AD5
         C7 |12    53| AD4
         C6 |13    52| AD3
         C5 |14    51| AD2
         C4 |15    50| AD1
         C3 |16    49| AD0
         C2 |17    48| RD7
         C1 |18    47| RD6
         C0 |19    46| RD5
    GND/DAC |20    45| RD4
    VDD/DAC |21    44| RD3
          G |22    43| RD2
          R |23    42| RD1
          B |24    41| RD0
       *INT |25    40| CD0
      *WAIT |26    39| CD1
    *HRESET |27    38| CD2
      MODE1 |28    37| CD3
      MODE0 |29    36| CD4
       *CSW |30    35| CD5
       *CSR |31    34| CD6
        CD7 |32    33| VBB
            +--------+

Frequency

DIP64
Set reader to FREQ, put black probe to GND, red probe to 63 and 64 to measure CPU clock

External links

V9958 page on Wikipedia

Files