8224: Difference between revisions

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DIP16
DIP16
         +---\/---+
         +---\/---+
   RESET | 1    40| Vcc
   RESET | 1    16| Vcc
   *RESIN | 2    39| XTAL1
   *RESIN | 2    15| XTAL1
   RDYIN | 3    38| XTAL2
   RDYIN | 3    14| XTAL2
   READY | 4    37| TANK
   READY | 4    13| TANK
     SYNC | 5    36| OSC
     SYNC | 5    12| OSC
  Ø2(TTL) | 6    35| Ø1
  Ø2(TTL) | 6    11| Ø1
   *STSTB | 7    34| Ø2
   *STSTB | 7    10| Ø2
     GND | 8   33| Vdd
     GND | 8     9| Vdd
         +--------+
         +--------+
</pre>
</pre>

Latest revision as of 15:04, 15 December 2021

Clock Generator and Driver

Pinout

DIP16
         +---\/---+
   RESET | 1    16| Vcc
  *RESIN | 2    15| XTAL1
   RDYIN | 3    14| XTAL2
   READY | 4    13| TANK
    SYNC | 5    12| OSC
 Ø2(TTL) | 6    11| Ø1
  *STSTB | 7    10| Ø2
     GND | 8     9| Vdd
         +--------+

Frequency

DIP16
Set reader to FREQ, put black probe to GND, red probe to 6,10,11,12 to measure output clocks

External links

Clock generator page on Wikipedia
8224 page on CPU-World

Files