SRAM 256 x 4: Difference between revisions

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Line 14: Line 14:
| American Semiconductors || EA || 2101 || 22 ||  || EA2101
| American Semiconductors || EA || 2101 || 22 ||  || EA2101
|-
|-
| Fairchild || F || 93422 || 22 || TS || F93422 F93422A F93422DC F93L422 F93L422A
| Fairchild || F || 93422 || DIP22-400mil || TS || F93422 F93422A F93422DC F93L422 F93L422A
|-
|-
| Harris || HM || 6551 || 22 ||  || HM6551
| Harris || HM || 6551 || 22 ||  || HM6551
Line 152: Line 152:
[[Category:DIP16]]
[[Category:DIP16]]
[[Category:DIP18]]
[[Category:DIP18]]
[[Category:DIP22]]
[[Category:DIP22-400mil]]
[[Category:DIP24]]
[[Category:DIP24]]

Revision as of 13:55, 17 March 2017

Cross-Reference
BRAND TAG NUMBER PIN COUNT OUTPUT MARKINGS
AMD AM 9101 22 AM9101 AM93422
AMD AM 9111 18 AM9111
American Semiconductors EA 2101 22 EA2101
Fairchild F 93422 DIP22-400mil TS F93422 F93422A F93422DC F93L422 F93L422A
Harris HM 6551 22 HM6551
Harris HM 6561 18 HM6561
Intel D/P 2101 22 TS D2101 D2101A
Intel D/P 2111 18 TS D2111
Intel D/P 2112 16 TS D2112
Intel D/P 2113 D2113
Intel D/P 5101 22 TS D5101 D5101L
Intel D/P 8101 22 TS D8101
Intel D/P 8111 18 TS D8111
Intersil MWS 5101 22 MWS5101 HM6551
Mitsubishi M5L 2111 18 M5L2111
Motorola MCM 5101 22 MCM5101
National Semiconductors MM 6551 22 MM6551 74C920 MM2101
Philips PCD 5101 22 PCD5101
Pyramid Semiconductor P4C 422 22 P4C422
Pyramid Semiconductor P4C 423 24 P4C422
Pyramid Semiconductor P4C 93U422 22 TS P93U422 P4C93U422
RCA CD 5101 22 CD5101 CD1822
Texas Instruments TMS 2101 22 TMS2101 TMS2102 TMS4039
Texas Instruments TMS 2111 18 TMS2111 TMS2112 TMS4042
Toshiba TMM 5101 22 TMM5101

Static Random-Access Memory 256 x 4 (DIP16, 300mil)(DIP18, 300mil)(DIP22, 300mil)(DIP24, 300mil)

Size

bit Byte (padded 0000xxxx) Byte (unpadded) Hex
1Kb 512B 256B 400hex

Pinout

DIP24
    +--\/--+
A2  |1   24| Vcc
A3  |2   23| A1
A4  |3   22| A0
A5  |4   21| *WE
A6  |5   20| *CS1
A7  |6   19| *OE
Vss |7   18| Vcc
D0  |8   17| CS2
D1  |9   16| D3
O0  |10  15| D2
O1  |11  14| O3
Vss |12  13| O2
    +------+

DIP22
    +--\/--+
A3  |1   22| Vcc
A2  |2   21| A4
A1  |3   20| *WE
A0  |4   19| *CS0
A5  |5   18| *OE
A6  |6   17| CS1
A7  |7   16| O3
GND |8   15| D3
D0  |9   14| O2
O0  |10  13| D2
D1  |11  12| O1
    +------+

DIP18
    +--\/--+
A3  |1   18| Vcc
A2  |2   17| A4
A1  |3   16| *WE
A0  |4   15| *CE1
A5  |5   14| O4
A6  |6   13| O3
A7  |7   12| O2
GND |8   11| O1
D0  |9   10| *CE2
    +------+

DIP16
    +--\/--+
A3  |1   16| Vcc
A2  |2   15| A4
A1  |3   14| *WE
A0  |4   13| *CE1
A5  |5   12| O4
A6  |6   11| O3
A7  |7   10| O2
GND |8    9| O1
    +------+

External links

SRAM page on wikipedia

Files