SRAM 256 x 4: Difference between revisions

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| Intel || D || 2101 || 22 || TS || I2101 I2101A 8101 8101A S5101
| Intel || D || 2101 || 22 || TS || I2101 I2101A 8101 8101A S5101
|-
|-
| Intel || D || 2111 || 18 || || 2111
| Intel || I || 2111 || 18 || TS || I2111
|-
| Intel || I || 2112 || 16 || TS || I2112
|-
|-
| Intersil || MWS || 5101 || 22 ||  || MWS5101 HM6551
| Intersil || MWS || 5101 || 22 ||  || MWS5101 HM6551
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|}
|}


'''Static Random-Access Memory 256 x 4 (DIP18, 300mil)(DIP22, 300mil)'''
'''Static Random-Access Memory 256 x 4 (DIP16, 300mil)(DIP18, 300mil)(DIP22, 300mil)'''


=Size=
=Size=
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A5  |5  14| O4
A5  |5  14| O4
A6  |6  13| O3
A6  |6  13| O3
A7  |7  12| 02
A7  |7  12| O2
GND |8  11| O1
GND |8  11| O1
D0  |9  10| *CE2
D0  |9  10| *CE2
     +------+
     +------+
</pre>
 
DIP16
    +--\/--+
A3  |1  16| Vcc
A2  |2  15| A4
A1  |3  14| *WE
A0  |4  13| *CE1
A5  |5  12| O4
A6  |6  11| O3
A7  |7  10| O2
GND |8    9| O1
    +------+</pre>


=External links=
=External links=
Line 94: Line 107:
File:am9111.pdf|AM9111 Datasheet
File:am9111.pdf|AM9111 Datasheet
File:2101A.pdf|2101A Datasheet
File:2101A.pdf|2101A Datasheet
File:i2111.pdf|I2111 Datasheet
File:i2112A.pdf|I2112A Datasheet
File:mws5101.pdf|MWS5101 Datasheet
File:mws5101.pdf|MWS5101 Datasheet
File:93l422.pdf|93L422 Datasheet
File:93l422.pdf|93L422 Datasheet

Revision as of 18:08, 16 January 2017

Cross-Reference
BRAND TAG NUMBER PIN COUNT OUTPUT MARKINGS
AMD AM 9101 22 AM9101 AM93422
AMD AM 9111 18 AM9111
American Semiconductors EA 2101 22 EA2101
Fairchild F 93422 22 F93422
Harris HM 6551 22 HM6551
Harris HM 6561 18 HM6561
Intel D 2101 22 TS I2101 I2101A 8101 8101A S5101
Intel I 2111 18 TS I2111
Intel I 2112 16 TS I2112
Intersil MWS 5101 22 MWS5101 HM6551
Mitsubishi M5L 2111 18 M5L2111
Motorola MCM 5101 22 MCM5101
National Semiconductors MM 6551 22 MM6551 74C920 MM2101
Philips PCD 5101 22 PCD5101
RCA CD 5101 22 CD5101 CD1822
Texas Instruments TMS 2101 22 TMS2101 TMS2102 TMS4039
Texas Instruments TMS 2111 18 TMS2111 TMS2112 TMS4042
Toshiba TMM 5101 22 TMM5101

Static Random-Access Memory 256 x 4 (DIP16, 300mil)(DIP18, 300mil)(DIP22, 300mil)

Size

bit Byte (padded 0000xxxx) Byte (unpadded) Hex
1Kb 512B 256B 400hex

Pinout

DIP22
    +--\/--+
A3  |1   22| Vcc
A2  |2   21| A4
A1  |3   20| *WE
A0  |4   19| *CS0
A5  |5   18| *OE
A6  |6   17| CS1
A7  |7   16| O3
GND |8   15| D3
D0  |9   14| O2
O0  |10  13| D2
D1  |11  12| O1
    +------+

DIP18
    +--\/--+
A3  |1   18| Vcc
A2  |2   17| A4
A1  |3   16| *WE
A0  |4   15| *CE1
A5  |5   14| O4
A6  |6   13| O3
A7  |7   12| O2
GND |8   11| O1
D0  |9   10| *CE2
    +------+

DIP16
    +--\/--+
A3  |1   16| Vcc
A2  |2   15| A4
A1  |3   14| *WE
A0  |4   13| *CE1
A5  |5   12| O4
A6  |6   11| O3
A7  |7   10| O2
GND |8    9| O1
    +------+

External links

SRAM page on wikipedia

Files

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