8255: Difference between revisions

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[[Category:CPU]]
[[Category:Other Chips]]
[[Category:DIP40]]
[[Category:DIP40]]

Revision as of 11:51, 23 October 2009

Programmable Peripheral Interface

Pinout

DIP40
         +---\/---+
     PA3 | 1    40| PA4
     PA2 | 2    39| PA5
     PA1 | 3    38| PA6
     PA0 | 4    37| PA7
     *RD | 5    36| *WR
     *CS | 6    35| RESET
     GND | 7    34| D0
      A1 | 8    33| D1
      A0 | 9    32| D2
     PC7 |10    31| D3
     PC6 |11    30| D4
     PC5 |12    29| D5
     PC4 |13    28| D6
     PC0 |14    27| D7
     PC1 |15    26| Vcc
     PC2 |16    25| PB7
     PC3 |17    24| PB6
     PB0 |18    23| PB5
     PB1 |19    22| PB4
     PB2 |20    21| PB3
         +--------+

Frequency

No frequency to check

External links

Files