V30: Difference between revisions

From Citylan
Jump to navigationJump to search
 
(3 intermediate revisions by the same user not shown)
Line 18: Line 18:
     AD4 |12    29| *WR (BUSLOCK)
     AD4 |12    29| *WR (BUSLOCK)
     AD3 |13    28| *IO/M (BS2)
     AD3 |13    28| *IO/M (BS2)
     AD2 |14    27| *BUFR/W (BS1)
     AD2 |14    27| BUF *R/W (BS1)
     AD1 |15    26| *BUFEN (BS0)
     AD1 |15    26| *BUFEN (BS0)
     AD0 |16    25| ASTB (QS0)
     AD0 |16    25| ASTB (QS0)
Line 33: Line 33:


=External links=
=External links=
[http://en.wikipedia.org/wiki/V30 V30 page on Wikipedia]<br>
[http://en.wikipedia.org/wiki/NEC_V20#V30 V30 page on Wikipedia]<br>
[http://www.cpu-world.com/CPUs/V30/index.html V30 page on CPU-World]
[http://www.cpu-world.com/CPUs/V30/index.html V30 page on CPU-World]


=Files=
=Files=
<gallery widths="150px">
<gallery widths="150px">
File:v30.pdf|V30 Datasheet
</gallery>
</gallery>


[[Category:CPU]]
[[Category:CPU]]
[[Category:DIP40]]
[[Category:DIP40-600mil]]

Latest revision as of 15:32, 9 November 2017

16-bit Microprocessor

Pinout

DIP40
         +---\/---+
      IC | 1    40| Vdd
    AD14 | 2    39| AD15
    AD13 | 3    38| A16/PS0
    AD12 | 4    37| A17/PS1
    AD11 | 5    36| A18/PS2
    AD10 | 6    35| A19/PS3
     AD9 | 7    34| *UBE
     AD8 | 8    33| S/*LG
     AD7 | 9    32| *RD
     AD6 |10    31| HLDRQ (*RQ/*AK0)
     AD5 |11    30| HLDAK (*RQ/*AK1)
     AD4 |12    29| *WR (BUSLOCK)
     AD3 |13    28| *IO/M (BS2)
     AD2 |14    27| BUF *R/W (BS1)
     AD1 |15    26| *BUFEN (BS0)
     AD0 |16    25| ASTB (QS0)
     NMI |17    24| *INTAK (QS1)
     INT |18    23| *POLL
     CLK |19    22| READY
     GND |20    21| RESET
         +--------+

Frequency

DIP40
Set reader to FREQ, put black probe to GND, red probe to 19 to measure CPU clock

External links

V30 page on Wikipedia
V30 page on CPU-World

Files