SRAM 256 x 8: Difference between revisions

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{| style="float: right;" border="1" cellpadding="4" cellspacing="0"
{| style="float: right;" border="1" cellpadding="4" cellspacing="0" class="sortable"
|+ style="background:silver" | Cross-Reference
|+ style="background:silver" | Cross-Reference
!BRAND
!BRAND
!TAG
!TAG
!NUMBER
!NUMBER
!PIN COUNT
!OUTPUT
!MARKINGS
!MARKINGS
|-
|-
| Intel || D/P || 8155 8156 || D8155 D8155H D8156 D8156H
| Intel || D/P || 8155 || 40 || . || D8155 D8155H
|-
| Intel || D/P || 8156 || 40 || . || D8156 D8156H
|}
|}


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=Files=
=Files=
<gallery widths="150px">
<gallery widths="150px">
File:d8155h.pdf|D8155H Datasheet
File:d8155h.pdf|D8155H D8156H Datasheet
</gallery>
</gallery>


[[Category:RAM]]
[[Category:RAM]]
[[Category:DIP40]]
[[Category:DIP40-600mil]]

Latest revision as of 15:46, 9 November 2017

Cross-Reference
BRAND TAG NUMBER PIN COUNT OUTPUT MARKINGS
Intel D/P 8155 40 . D8155 D8155H
Intel D/P 8156 40 . D8156 D8156H

Static Random-Access Memory 256 x 8 (DIP40, 600mil)

Size

bit Byte Hex
2Kb 256B 800hex

Pinout

DIP40
           +--\/--+
       PC3 |1   40| Vcc
       PC4 |2   39| PC2
  TIMER IN |3   38| PC1
     RESET |4   37| PC0
       PC5 |5   36| PB7
*TIMER OUT |6   35| PB6
     IO/*M |7   34| PB5
       *CE |8   33| PB4
       *RD |9   32| PB3
       *WR |10  31| PB2
       ALE |11  30| PB1
       AD0 |12  29| PB0
       AD1 |13  28| PA7
       AD2 |14  27| PA6
       AD3 |15  26| PA5
       AD4 |16  25| PA4
       AD5 |17  24| PA3
       AD6 |18  23| PA2
       AD7 |19  22| PA1
       Vss |20  21| PA0
           +------+

External links

SRAM page on wikipedia

Files