Um8272: Difference between revisions

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m (Created page with '<gallery widths="150px"> File:um8272.pdf|Datasheet </gallery> Category:CPU')
 
 
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'''Floppy Disk Controller'''
=Pinout=
<pre>
DIP40
        +---\/---+
  RESET | 1    40| Vcc
    *RD | 2    39| *RW/SEEK
    *WR | 3    38| LCT/DIR
    *CS | 4    37| FR/STP
      A0 | 5    36| HDL
    DB0 | 6    35| RDY
    DB1 | 7    34| WP/TS
    DB2 | 8    33| FLT/TRK0
    DB3 | 9    32| PS0
    DB4 |10    31| PS1
    DB5 |11    30| WDA
    DB6 |12    29| DS0
    DB7 |13    28| DS1
    DRQ |14    27| SEL
  *DACK |15    26| MFM
      TC |16    25| WE
    IDX |17    24| VCO
    INT |18    23| RD DATE
    CLK |19    22| RDW
    GND |20    21| WR CLK
        +--------+
</pre>
=Frequency=
'''DIP40'''<br>
Set reader to FREQ, put black probe to GND, red probe to 19 to measure CPU clock
=External links=
=Files=
<gallery widths="150px">
<gallery widths="150px">
File:um8272.pdf|Datasheet
File:um8272.pdf|UM8272 Datasheet
</gallery>
</gallery>


[[Category:CPU]]
[[Category:Other Chips]]
[[Category:DIP40-600mil]]

Latest revision as of 15:34, 9 November 2017

Floppy Disk Controller

Pinout

DIP40
         +---\/---+
   RESET | 1    40| Vcc
     *RD | 2    39| *RW/SEEK
     *WR | 3    38| LCT/DIR
     *CS | 4    37| FR/STP
      A0 | 5    36| HDL
     DB0 | 6    35| RDY
     DB1 | 7    34| WP/TS
     DB2 | 8    33| FLT/TRK0
     DB3 | 9    32| PS0
     DB4 |10    31| PS1
     DB5 |11    30| WDA
     DB6 |12    29| DS0
     DB7 |13    28| DS1
     DRQ |14    27| SEL
   *DACK |15    26| MFM
      TC |16    25| WE
     IDX |17    24| VCO
     INT |18    23| RD DATE
     CLK |19    22| RDW
     GND |20    21| WR CLK
         +--------+

Frequency

DIP40
Set reader to FREQ, put black probe to GND, red probe to 19 to measure CPU clock

External links

Files