DRAM 64k x 4: Difference between revisions

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SRAM 64K x 4 (DIP28, 300mil)
{| style="float: right;" border="1" cellpadding="4" cellspacing="0" class="sortable"
|+ style="background:silver" | Cross-Reference
!BRAND
!TAG
!NUMBER
!PIN COUNT
!OUTPUT
!MARKINGS
|-
|Fujitsu || MB || 81464 || DIP18 LCC18 ZIP20 ||TS || MB81464
|-
|Fujitsu || MB || 81466 || DIP18 || || MB81466
|-
|Hitachi || HM || 50464 || DIP18 || || HM50464
|-
|Hitachi || HM || 53461 || DIP24 ZIP24 || || HM53461P HM53461ZP
|-
|Matsushita || MN || 41464 || DIP18 || || MN41464
|-
|Mitsubishi || M5M || 4464 || DIP18 || || M5M4464
|-
|Mitsubishi || M5M || 4C264 || ZIP24 || || M5M4C264 M5M4C264L
|-
|NEC || uPD || 41464 || DIP18 || || uPD41464 D41464 D41464C
|-
|OKI || MSM || 41464 || DIP18 || || MSM41464
|-
|Samsung || KM || 41464 || DIP18 LCC18 ZIP20 || || KM41C464 KM41464A
|-
|Samsung || KM || 41466 || DIP18 || || KM41C466
|-
|Sharp || LH || 2464 || DIP18 || || LH2464
|-
|Texas Instruments || TMS || 4464 || DIP18 || || TMS4464
|-
|Toshiba || TC || 51464 || DIP18 || || TC51464
|-
|Toshiba || TC || 51466 || DIP18 || || TC51466
|-
|Zentrum Mikroelektronik || UD || 61464 || DIP18 || TS || UD61464
|-
|Note:
*464= Page mode
*466= Static column mode
||  ||  || ||  ||
|}


256Kb, 32KB, 10000hex4 bit
'''Dynamic Random-Access Memory 64K x 4 (DIP18, 300mil)(DIP24, 400mil)(LCC18, 330mil)(ZIP20, 100mil)(ZIP24, 100mil)'''


pinout
=Size=
{| border="1" cellpadding="4" cellspacing="0"
|-align="left"
!bit
!Byte (padded 0000xxxx)
!Byte (unpadded)
!Hex
|-
|256Kb || 64KB || 32KB || 40000hex
|}
 
=Pinout=
<pre>
<pre>
     +--\/--+
DIP18
A6  |1   28| Vcc
        +---\/---+
A7  |2   27| A5
    *OE | 1    18| Vss
A8  |3   26| A4
    DO1 | 2    17| D04
A9 |4   25| A3
    DO2 | 3    16| *CAS
A10 |5   24| A2
    *WE | 4    15| DO3
A11 |6   23| A1
     *RAS | 5    14| A0
A12 |7   22| A0
      A6 | 6    13| A1
A13 |8   21| I3
      A5 | 7    12| A2
A14 |9   20| I2
      A4 | 8    11| A3
A15 |10  19| 03
    Vcc | 9    10| A7
I0 |11 18| 02
        +--------+
I1 |12 17| 01
 
CE/ |13 16| O0
DIP24
GND |14 15| WE/
        +---\/---+
    +------+</pre>
      SC | 1   24| Vss
  SI/O1 | 2   23| SI/O4
  SI/O2 | 3   22| SI/O3
  *DT/*OE | 4   21| *SEO
    I/O1 | 5   20| I/O4
    I/O2 | 6   19| I/O3
    *WE | 7   18| *CAS
    *RAS | 8   17| A0
      A6 | 9   16| A1
      A5 |10   15| A2
      A4 |11    14| A3
    Vcc |12    13| A7
        +--------+
 
LCC18
+---------------------------------------------------------------+
| 3 DO2        |  8 A4        | 12 A2        | 17 D04        |
| 4 *WE        |  9 Vcc        | 13 A1        | 18 Vss        |
| 5 *RAS      | 10 A7        | 14 A0        |  1 *OE        |
|  6 A6        | 11 A3        | 15 DO3        |  2 DO1        |
|  7 A5        |              | 16 *CAS      |              |
+---------------------------------------------------------------+
 
 
ZIP20
          ^
  DO3  1 |
          |  2 *CAS
  DO4  3 |
          |  4 Vss
  *OE  5 |
          |  6 DO1
  DO2  7 |
          |  8 *WE
  *RAS  9 |
          | 10 NC
    NC 11 |
          | 12 A6
    A5 13 |
          | 14 A4
  Vcc 15 |
          | 16 A7
    A3 17 |
          | 18 A2
    A1 19 |
          | 20 A0
          -
 
 
ZIP24
          ^
W2/IO2  1 |
          |  2 W3/IO3
  *SE  3 |
          |  4 SIO2
  SIO3  5 |
          |  6 Vss
    SC  7 |
          |  8 SIO0
  SIO1  9 |
          | 10 *DT/*OE
W0/IO0 11 |
          | 12 W1/IO1
*WB/WE 13 |
          | 14 *RAS
    A6 15 |
          | 16 A5
    A4 17 |
          | 18 Vcc
    A7 19 |
          | 20 A3
    A4 21 |
          | 22 A1
    A7 23 |
          | 24 *CAS
          -
</pre>
 
=External links=
[http://en.wikipedia.org/wiki/Dynamic_random-access_memory DRAM page on wikipedia]


[[Image:dip28-300mil.jpg]]
=Files=
<gallery widths="150px">
File:hm53461.pdf|HM53461 Datasheet
File:km41464A.pdf|KM41464A Datasheet
File:m5m4c264.pdf|M5M4C264 Datasheet
File:mb81464.pdf|MB81464 Datasheet
File:ud61464.pdf|UD61464 Datasheet
</gallery>


[[Category:RAM]]
[[Category:RAM]]
[[Category:DIP28]]
[[Category:DIP18-300mil]]
[[Category:DIP24-400mil]]
[[Category:LCC18-290x490mil]]
[[Category:ZIP20]]
[[Category:ZIP24]]

Latest revision as of 08:59, 20 February 2024

Cross-Reference
BRAND TAG NUMBER PIN COUNT OUTPUT MARKINGS
Fujitsu MB 81464 DIP18 LCC18 ZIP20 TS MB81464
Fujitsu MB 81466 DIP18 MB81466
Hitachi HM 50464 DIP18 HM50464
Hitachi HM 53461 DIP24 ZIP24 HM53461P HM53461ZP
Matsushita MN 41464 DIP18 MN41464
Mitsubishi M5M 4464 DIP18 M5M4464
Mitsubishi M5M 4C264 ZIP24 M5M4C264 M5M4C264L
NEC uPD 41464 DIP18 uPD41464 D41464 D41464C
OKI MSM 41464 DIP18 MSM41464
Samsung KM 41464 DIP18 LCC18 ZIP20 KM41C464 KM41464A
Samsung KM 41466 DIP18 KM41C466
Sharp LH 2464 DIP18 LH2464
Texas Instruments TMS 4464 DIP18 TMS4464
Toshiba TC 51464 DIP18 TC51464
Toshiba TC 51466 DIP18 TC51466
Zentrum Mikroelektronik UD 61464 DIP18 TS UD61464
Note:
  • 464= Page mode
  • 466= Static column mode

Dynamic Random-Access Memory 64K x 4 (DIP18, 300mil)(DIP24, 400mil)(LCC18, 330mil)(ZIP20, 100mil)(ZIP24, 100mil)

Size

bit Byte (padded 0000xxxx) Byte (unpadded) Hex
256Kb 64KB 32KB 40000hex

Pinout

DIP18
         +---\/---+
     *OE | 1    18| Vss
     DO1 | 2    17| D04
     DO2 | 3    16| *CAS
     *WE | 4    15| DO3
    *RAS | 5    14| A0
      A6 | 6    13| A1
      A5 | 7    12| A2
      A4 | 8    11| A3
     Vcc | 9    10| A7
         +--------+

DIP24
         +---\/---+
      SC | 1    24| Vss
   SI/O1 | 2    23| SI/O4
   SI/O2 | 3    22| SI/O3
 *DT/*OE | 4    21| *SEO
    I/O1 | 5    20| I/O4
    I/O2 | 6    19| I/O3
     *WE | 7    18| *CAS
    *RAS | 8    17| A0
      A6 | 9    16| A1
      A5 |10    15| A2
      A4 |11    14| A3
     Vcc |12    13| A7
         +--------+

LCC18
+---------------------------------------------------------------+
|  3 DO2        |  8 A4         | 12 A2         | 17 D04        |
|  4 *WE        |  9 Vcc        | 13 A1         | 18 Vss        |
|  5 *RAS       | 10 A7         | 14 A0         |  1 *OE        |
|  6 A6         | 11 A3         | 15 DO3        |  2 DO1        |
|  7 A5         |               | 16 *CAS       |               |
+---------------------------------------------------------------+


ZIP20
          ^
   DO3  1 |
          |  2 *CAS
   DO4  3 |
          |  4 Vss
   *OE  5 |
          |  6 DO1
   DO2  7 |
          |  8 *WE
  *RAS  9 |
          | 10 NC
    NC 11 |
          | 12 A6
    A5 13 |
          | 14 A4
   Vcc 15 |
          | 16 A7
    A3 17 |
          | 18 A2
    A1 19 |
          | 20 A0
          -


ZIP24
          ^
W2/IO2  1 |
          |  2 W3/IO3
   *SE  3 |
          |  4 SIO2
  SIO3  5 |
          |  6 Vss
    SC  7 |
          |  8 SIO0
  SIO1  9 |
          | 10 *DT/*OE
W0/IO0 11 |
          | 12 W1/IO1
*WB/WE 13 |
          | 14 *RAS
    A6 15 |
          | 16 A5
    A4 17 |
          | 18 Vcc
    A7 19 |
          | 20 A3
    A4 21 |
          | 22 A1
    A7 23 |
          | 24 *CAS
          -

External links

DRAM page on wikipedia

Files

  • HM53461 Datasheet

    HM53461 Datasheet

  • KM41464A Datasheet

    KM41464A Datasheet

  • M5M4C264 Datasheet

    M5M4C264 Datasheet

  • MB81464 Datasheet

    MB81464 Datasheet

  • UD61464 Datasheet

    UD61464 Datasheet

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